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F28M36P63C2
(ACTIVE) F28M36Px Concerto 微处理器

 

说明
The Concerto™ family is a multi-core system-on-chip microcontroller (MCU) with independent communication and real-time control subsystems. The F28M36x is the second series in the Concerto family.

The communications subsystem is based on the industry-standard 32-bit ARM® Cortex™-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, CAN, UART, SSI, I2C, and an external interface.

The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x™ Floating-Point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures—all as implemented by TI’s C2000™ Piccolo™ and Delfino™ families. In addition, the C28-CPU has been enhanced with the addition of the Viterbi, Complex Math, CRC Unit (VCU) instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs and CRC algorithms.

A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), Parity, and Code Secure Memory, as well as documentation to assist with system-level industrial safety certification.

特性

Master Subsystem — ARM® Cortex™-M3125 MHz
 Cortex™-M3 Core Hardware Logic Built-in Self Test
 Embedded Memory Up to 1MB Flash (ECC)
Up to 128KB RAM (ECC or Parity)
Up to 64KB Shared RAM
2KB IPC Message RAM

 5 Universal Asynchronous Receiver/Transmitters (UARTs)
 4 Synchronous Serial Interfaces (SSIs)/
 Serial Peripheral Interface (SPI)
 2 Inter-integrated Circuits (I2Cs)
 Universal Serial Bus On-the-Go (USB-OTG) + PHY
 10/100 ENET 1588 MII
 2 Controller Area Networks (CANs)
 32-Channel Direct Memory Access (µDMA)
 Dual Security Zones (128-Bit Password per Zone)
 External Peripheral Interface (EPI)
 Micro Cyclic Redundancy Check (µCRC) Module
 4 General-Purpose Timers
 2 Watchdog Timer Modules
 Endianness: Little Endian
 
ClockingOn-chip Crystal Oscillator/External Clock Input
 Dynamic PLL Ratio Changes Supported
 
1.2-V Digital, 1.8-V Analog, 3.3-V I/O Design
Interprocessor Communications (IPC)32 Handshaking Channels
 4 Channels Generate IPC Interrupts
 Can be Used to Coordinate Transfer of Data Through IPC Message RAMs
 
Up to 142 Individually Programmable, Multiplexed GPIO PinsGlitch-free I/Os
 
Control Subsystem — TMS320C28x™ 32-Bit CPU150 MHz
 C28x Core Hardware Logic Built-in Self Test
 Embedded Memory Up to 512KB Flash (ECC)
 Up to 36KB RAM (ECC or Parity)
 Up to 64KB Shared RAM
 2KB IPC Message RAM
 
IEEE-754 Single-Precision Floating-Point Unit (FPU)
 Viterbi, Complex Math, CRC Unit (VCU)
 Serial Communications Interface (SCI)
 Serial Peripheral Interface (SPI)
 Inter-Integrated Circuit (I2C)
 6-Channel Direct Memory Access (DMA)
 12 Enhanced Pulse Width Modulator (ePWM) Modules 24 Outputs (16 High-Resolution)
 
6 32-Bit Enhanced Capture (eCAP) Modules
 3 32-Bit Enhanced Quadrature Encoder (eQEP) Modules
 Multichannel Buffered Serial Port (McBSP)
 External Peripheral Interface (EPI)
 One Security Zone (128-Bit Password)
 3 32-Bit Timers
 Endianness: Little Endian
 
Analog SubsystemDual 12-Bit Analog-to-Digital Converters (ADCs)
 Up to 2.88 MSPS
 Up to 24 Channels
 4 Sample-and-Hold (S/H) Circuits
 Up to 6 Comparators With 10-Bit Digital-to-Analog Converter (DAC)

Package289-Ball ZWT Plastic Ball Grid Array (PBGA)